Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Most advanced logic and memory devices fabricated at semiconductor device fabrication nodes below 20 nanometers are constructed using multiple patterning processes. Exemplary multiple patterning processes include self-aligned double patterning (SADP), self-aligned triple patterning (SATP), and self-aligned quadruple patterning (SAQP) techniques.
In one example, a SAQP fin formation process achieves a target pitch that is one-quarter of the pitch obtainable with conventional single pattern lithography. In one example, at least fourteen steps are required to generate the fin structures. These steps include lithography, etch, and strip steps that must be precisely controlled to realize the fin structures with the desired pitch and profile. The final pitch values and fin profile (e.g. CD, SWA) achieved by the SAQP fin formation process are impacted by structural parameter values from previous steps (e.g., resist profile parameters, spacer film thicknesses, and others).
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput without the risk of sample destruction. A number of optical metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition, overlay and other parameters of nanoscale structures.
In some examples, optical critical dimension (CD) and film metrologies (spectroscopic or angle-resolved) are employed to monitor structural parameter values during multiple patterning processes to ensure that structures are fabricated having the desired pitch and profile. However, optical CD and film metrologies suffer from lack of sensitivity to many structures employed in multiple patterning techniques, buried structures, in particular. For some structural parameters, such as edge placement error (EPE), there is currently no high throughput (e.g., optical) measurement solution.
In another example, optical overlay metrology is also employed, but optical overlay measurements require specialized metrology targets to characterize structures fabricated by multiple patterning techniques. In existing methods, overlay error is typically evaluated based on measurements of specialized target structures formed at various locations on the wafer by a lithography tool. The target structures may take many forms, such as a box in box structure. In this form, a box is created on one layer of the wafer and a second, smaller box is created on another layer. The localized overlay error is measured by comparing the alignment between the centers of the two boxes. Such measurements are taken at locations on the wafer where target structures are available.
Unfortunately, these specialized target structures often do not conform to the design rules of the particular semiconductor manufacturing process being employed to generate the electronic device. This leads to errors in estimation of overlay errors associated with actual device structures that are manufactured in accordance with the applicable design rules. For example, image-based overlay metrology often requires the pattern to be resolved with an optical microscope that requires thick lines with critical dimensions far exceeding design rule critical dimensions. In another example, angle-resolved SCOL often requires large pitch targets to generate sufficient signal at the +1 and −1 propagating diffraction orders from the overlay targets. In some examples, pitch values in the range 500-800 nm may be used. Meanwhile, actual device pitches for logic or memory applications (design rule dimensions) may be much smaller, e.g., in the range 100-400 nm, or even below 100 nm.
FIG. 1 depicts a hardmask pattern of line structures 11 fabricated in a static random access memory (SRAM) area 10 of a microelectronic chip. The complex layout of the active region is created by combining multiple patterning techniques with cut masks. Cut masks selectively remove portions of the hardmask layer that is used to pattern the substrate into active regions. FIG. 2 depicts a bottom anti-reflective coating (BARC) layer 12 and a resist layer 13 disposed on top of the pattern of line structures depicted in FIG. 1. The resist layer is used to selectively remove part of the hardmask pattern below the openings 14 of the resist layer 13. As depicted in FIG. 1, the hardmask pattern of line structures 11 is buried by the BARC layer 12, even within the openings 14 of the resist layer 13.
To provide adequate yield for the cut mask process, reliable measurements for profile (e.g., CD, HT, SWA) film thicknesses, and overlay are required. A calculation of overlay reveals that it is a function of many structural parameters from previous steps of a quadruple patterning process. The distribution of the gap between the edge of the cut and the adjacent line structure, and hence the yield of the process, depends on a complex interaction of all the process parameters.
In another example, edge placement distance (EPD) and the associated edge placement error (EPE) is an important parameter to monitor and control after device electrical contacts are made. The difference between the desired and the actual EPD is called EPE. EPD and EPE are a function of both overlay and CD errors.
In some examples, critical dimension-scanning electron microscopy (CD-SEM) may be employed to measure overlay and EPE. However, most advanced process nodes require small metrology errors and high throughput that are not achievable with CD-SEM tools.
In summary, semiconductor device yield at device fabrication nodes below 20 nanometers for logic devices and advanced DRAM, and vertical or planar NAND devices is a complex function of many parameters, including film thicknesses, profile parameters of patterned lines, overlay errors, and edge placement errors (EPE). Of these, EPE has the most demanding process window and requires metrology and control of CD and overlay. Currently there is no high-throughput, optical metrology solution for EPE measurements and many on-device overlay measurement applications. In addition, the absence of adequate metrology makes it challenging to define control schemes to improve device yield.